1. Field of the Invention
The present invention relates to a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-073287, filed Mar. 26, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, with miniaturization of semiconductor devices, the plane area of semiconductor elements and regions in which transistors are formed (active regions) have been decreased. Regarding planar transistors, the channel length and width have been decreased with a decrease in the size of the active regions, and thereby the short channel effect and the like have been problematic.
For this reason, in lieu of planar transistors, semiconductor devices including vertical transistors, which achieve a sufficient channel length and width even in a miniaturized region, have been proposed.
Different from the planar transistor, the vertical transistor includes a pillar extending in a direction perpendicular to a main surface of the semiconductor substrate. In the on-state, a channel is formed along the pillar in a direction perpendicular to the main surface of the semiconductor substrate. Accordingly, the vertical transistor is more effectively applicable to a miniaturized semiconductor memory element, such as a DRAM, than the planar transistor.
A buried bit line is connected to a source and/or drain (S/D) region of a vertical transistor included in a semiconductor device. There is a buried bit line buried in a trench, an inner surface of which is covered by an insulating film. The buried bit line is connected to a diffusion layer, which forms an S/D region of a transistor, via a contact portion made of a conductive material, which is provided adjacent to a sidewall of the trench.
As a method of forming such a buried bit line, for example, a bit line trench, which extends in an extending direction of a bit line, is formed in a silicon substrate. Then, a silicon oxide film is formed so as to cover a side surface of the bit line trench that exposes the silicon substrate. Then, one of the side surfaces of the bit line trench is exposed. Then, a bottom portion of the bit line trench is filled with a material for forming a bit line. Thus, a bit line, which contacts the exposed portion of the silicon substrate, is formed. Then, a thermal treatment is carried out to diffuse an impurity from the bit line toward the exposed silicon substrate. Thus, a diffusion layer, which will become an S/D region, is formed (see, for example, Japanese Patent Laid-Open Publication No. 2009-10366).
However, regarding the semiconductor device of the related art, which includes the buried bit line contacting the lower diffusion layer, a variation of a capacitance value of the lower diffusion layer is large, and thereby the reliability of the semiconductor device is insufficient.
Hereinafter, problems of the semiconductor device of the related art are explained with accompanying drawings. FIG. 22 is a cross-sectional view illustrating part of a semiconductor memory device, such as a DRAM (Dynamic Random Access Memory), which is an example of the semiconductor device of the related art. FIGS. 23 to 30 are cross-sectional views illustrating a process flow indicative of a method of the related art for manufacturing the DRAM shown in FIG. 22. FIG. 31 is a plan view illustrating one process included in the method of the related art for manufacturing the DRAM shown in FIG. 22.
Regarding the semiconductor memory device of the related art, which is shown in FIG. 22, trenches 202a and 202b are formed in a semiconductor substrate 200 made of silicon. Thus, silicon pillars 203a, 203b, and 203c are defined by the trenches 202a and 202b. The silicon pillars 203a, 203b, and 203c become channels of a transistor.
A pair of gate electrodes 208a and 208b is buried so as to cover both side surfaces of the silicon pillar 203a. Similarly, a pair of gate electrodes 208c and 208d is buried so as to cover both side surfaces of the adjacent silicon pillar 203b. The gate electrodes 208a, 208b, 208c, and 208d function as word lines.
An insulating film 204, which is made of a thermal oxide film, is formed so as to cover inner surfaces of bottom portions 201a and 201b of the trenches 202a and 202b. Buried bit lines 205a and 205b are formed over the insulating film 204 so as to fill the bottom portions 201a and 201b. The extending direction of the bit lines 205a and 205b is perpendicular to the extending direction of the word lines (the gate electrodes 208a, 208b, 208c, and 208d shown in FIG. 22). The buried bit lines 205a and 205b are connected to lower diffusion layers 206a and 206b via contact portions 13a and 13b, respectively. The lower diffusion layers 206a and 206b are S/D regions of a transistor.
Upper diffusion layers 210 are formed in upper surface regions of the silicon pillars 203a, 203b, and 203c. The upper diffusion layers 210 are other S/D regions. Contact plugs 212 are formed over the upper diffusion layers 210. A capacitor 213 is formed over the contact plugs 212. The capacitor 213 includes a lower electrode 213a, a capacitor insulating film 213b, and an upper electrode 213c. The silicon pillars 203a, 203b, and 203c are isolated from one another by an inter-layer insulating film 209. The contact plugs 212 are isolated from one another by an inter-layer insulating film 211.
Regarding the silicon pillar 203b, one transistor is formed, which includes: the lower diffusion layer 206b connected to the bit line 205b; a pair of the gate electrodes 208c and 208d covering side surfaces of the silicon pillar 203b via a gate insulating film (not shown in FIG. 22); and the upper diffusion layer 210 connected to the capacitor 213.
Hereinafter, a method of manufacturing the semiconductor memory device shown in FIG. 22 is explained with reference to FIGS. 23 to 31. Firstly, a silicon nitride film 140 is formed over a semiconductor substrate 200 made of silicon. Then, holes 105c are formed in the silicon nitride film 140 by photolithography and dry-etching processes so as to partially expose an upper surface of the semiconductor substrate 200, as shown in FIG. 23.
Then, the semiconductor substrate 200 is anisotropically dry-etched with the silicon nitride film 140 as a mask to form the trenches 202a and 202b. Then, the insulating film 204, which is made of a thermal oxide film, is formed so as to cover inner surfaces of the trenches 202a and 202b, as shown in FIG. 24.
Then, a poly-silicon film 111 is formed over the insulating film 204 by a CVD (Chemical Vapor Deposition) method so as to fill the trenches 202a and 202b, as shown in FIG. 25. Then, the poly-silicon film 111 is dry-etched so that the top level of the poly-silicon film 111 becomes equal to the top level of the contact portions 13a and 13b (see FIG. 22).
Then, a sidewall 115, which has a different etching rate from that of the insulating film 204, is formed so as to cover portions of the insulating film 204 which cover the side surfaces of the trenches 202a and 202b. Then, the poly-silicon film 111 is dry-etched so that the top level of the poly-silicon film 111 becomes equal to the bottom level of the contact portions 13a and 13b (see FIG. 22), as shown in FIG. 26.
Then, a mask, which has a different etching rate from that of the insulating film 204, is formed so as to cover the sidewall 115 excluding a lower portion of the sidewall 115 which is positioned at the formation region of the contact portion 13a (13b). Then, the insulating film 204 is wet-etched with the mask. Thus, a hole 100a, which exposes part of the semiconductor substrate 200, is formed in the insulating film 204, as shown in FIG. 26.
Before the wet-etching process to form the hole 100a in the insulating film 204, a lithography process is carried out in order to cover contact portions 202aa and 202bb for pulling up bit lines with a photoresist film. The contact portions 202aa and 202bb are positioned at end portions of the bit line trenches 202a and 202b, as shown in FIG. 31.
If the holes 100a are formed also in portions of the insulating film 204 which cover the contact portions 202aa and 202bb, diffusion layers are formed adjacent to the contact portions 202aa and 202bb in a later process. Thereby, short-circuit occurs between adjacent bit lines. To prevent this problem, diffusion layers are prevented from being formed adjacent to the contact portions 202aa and 202bb. In other words, a lithography process is carried out, in which a photoresist film is formed so as to cover a memory cell region excluding a region in which a pillar transistor is formed. Thus, an opening pattern 202c is formed. Then, the hole 100a is formed in the insulating film 204 with the photoresist film having the opening pattern 202c. Then, the photoresist film is removed after the hole 100a is formed.
After the hole 100a is formed, the sidewall 115 is removed. Then, a poly-silicon film 117, which contains an impurity, such as arsenic or phosphorus, is formed over the silicon nitride film 140 by the CVD method so as to fill the trenches 202a and 202b, as shown in FIG. 27. Then, the poly-silicon film 117 is dry-etched so that only a portion of the poly-silicon film 117 which covers the hole 100a remains, and other portions of the poly-silicon film 117 are removed. Thus, the contact portions 13a and 13b are formed, as shown in FIG. 28.
Then, a conductive film 120, which is made of a conductive material, is formed by the CVD method over the silicon nitride film 140 so as to fill the trenches 202a and 202b, as shown in FIG. 29. Then, a thermal treatment process is carried out to diffuse an impurity included in the contact portions 13a and 13b into the semiconductor substrate 200. Thus, the lower diffusion layers 206a and 206b are formed.
Then, the conductive film 120 is anisotropically dry-etched down to the top level of the contact portions 13a and 13b. Thus, the buried bit lines 205a and 205b are formed as shown in FIG. 30. The buried bit lines 205a and 205b fill the bottom portions of the trenches 202a and 202b, and are connected to the lower diffusion layers 206a and 206b via the contact portions 13a and 13b, respectively.
Then, the gate electrodes 208a, 208b, 208c, and 208d (word lines) are formed above the bit lines 205a and 205b, as shown in FIG. 22. The extending direction of the gate electrodes 208a, 208b, 208c, and 208d is perpendicular to the extending direction of the bit lines 205a and 205b. 
Then, the silicon nitride film 140 is removed. Then, a process of forming the upper diffusion layers (S/D regions) 210 over the silicon pillars 203a, 203b, and 203c, a process of forming the contact plugs 212 over the upper diffusion layers 210, and a process of forming the capacitor 213 over the contact plugs 212 are carried out. Thus, the semiconductor device shown in FIG. 22 can be obtained.
Regarding the semiconductor device obtained by the above method, a thermal treatment process is carried out to diffuse the impurity included in the contact portions 13a and 13b with the small area into the semiconductor substrate 200 to form the lower diffusion layers 206a and 206b. For this reason, a variation of resistance values of the lower diffusion layers 206a and 206b is likely to become large.